1. Field of the Invention
The present invention relates to a data transmission unit for transmitting data after converting parallel data into serial data.
2. Description of Related Art
FIG. 12 is a block diagram showing a conventional asynchronous data transmission unit 100 embedded in a 16-bit single chip microcomputer M310002, for example. In this figure, the reference numeral 101 designates a TXD transmitted data output port for transferring transmitted data to a receiver 120, and 102 designates a CTS (Clear To Send) handshake signal input port for inputting a ready to accept signal 107 (see, FIG. 13) from the receiver 120.
FIG. 13 is a timing diagram of the data transmission, in which the reference numeral 103 designates a start bit added to the head of transmitted data 104 output from the TXD transmitted data output port 101, 104 designates the transmitted data itself, 105 designates a parity bit bearing parity information of the transmitted data, and 106 designates a stop bit indicating the end of the transmitted data 104.
Next, the operation will be described.
The data transmission unit 100, receiving a LOW level signal, that is, the ready to accept signal 107 from the receiver 120 at the CTS handshake signal input port 102, recognizes that the receiver 120 is ready for receiving, receives parallel data from a CPU, and starts transfer of the transmitted data 104 from the TXD transmitted data output port 101.
The start bit 103 indicating the start of the data transmission is output in front of the transmitted data 104. Then, the transmitted data 104 is output, followed by the output of the parity bit 105 indicating the parity information of the transmitted data at its end. Finally, the stop bit 106 is output indicating the end of the data transmission after the parity bit 105, thereby informing the receiver 120 of the end of the transmission.
FIG. 14 is a block diagram showing a conventional synchronous data transmission unit 130 for transmitting data in synchronism with a transfer clock signal. In this figure, the reference numeral 108 designates a transfer clock output port from which a transfer clock signal is transmitted to the receiver 120. The transfer clock signal is supplied from a clock generator 109 activated by the ready to accept signal 107 received at the CTS handshake signal input port 102.
FIG. 15 is a timing diagram of the data transmission, in which the reference numeral 110 designates an enabling bit for setting both the transmitter/receiver to transmission/reception enabled states, 111 designates a detection signal indicating the presence/absence of the transmitted data to the data transmission unit 130, and 113 designates a transfer clock signal output from the transfer clock output port 108.
Next, the operation will be described.
When the enabling bit 110 changes to enable the transmission/reception, the data transmission unit 130 is supplied with parallel data from the CPU 112, and awaits the ready to accept signal 107 from the receiver 120, that is, awaits the CTS handshake signal input port 102 to be supplied with a LOW level signal. When the CTS handshake signal is input, the clock generator 109 is activated so that the transfer clock signal 113 is sent from the transfer clock output port 108 to the receiver 120. Thus, the start of transfer of the transmitted data 104 from the TXD transmitted data output port 101 is synchronized with the start of reception at the receiver by the CTS handshake signal and the transfer clock signal.
Related art to such a conventional synchronous data transmission unit as shown in FIG. 14 is disclosed in Japanese patent applications laid-open Nos. 61-95648 (1986), 1-245737 (1989), 62-287736 (1987), for example.
The conventional asynchronous data transmission unit as shown in FIG. 12 has a problem in that high-speed data transmission cannot be achieved because it is necessary for the receiver 120 to detect the center of each bit of the received signal by counting so that sampling of each bit of the received signal is adjusted to take place at the center of each bit, although the transmitted data is provided with the start bit 103, the parity bit 105 and the stop bit 106 to increase its reliability.
On the other hand, the conventional synchronous data transmission unit has a problem in that although its transmission rate is higher than that of the asynchronous data transmission unit as shown in FIG. 12, the synchronization between the transmitter and the receiver must be carried out, which is rather tedious.